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this document is a general prod uct description and is subject to change without notice. hynix electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev 0 7 / apr. 2001 hynix semiconductor hy62 u 8400 a series 512kx8bit cmos sram document title 512k x8 bit 3.0v low power cmos slow sram revision history revision no history draft date remark 04 revision history insert jul.26.2000 final revised - insert 70ns part - improved standby curre nt isb1 : 30ua ?? 20ua 05 revised aug.04.2000 final - change iccdr value : 15 ua => 20ua 06 marking information add dec.04.2000 final revised - e.t ( - 25~85 c), i.t ( - 40~85 c) part insert - ac test condition add : 5pf test load - tclz value change : 15ns/20ns - > 10ns - v ih max : vcc + 0.2v => vcc + 0.3v - v il min : - 0.2v => - 0.3v 07 changed logo apr.30.2001 final - hyundai - > h ynix - marking information change
hy62 u 8400 a series rev 0 7 / apr. 2001 2 description the hy62 u 8400 a is a high - speed, low power and 4m bits cmos sram organized as 512k words by 8 b its. the hy62 u 8400 a uses hynix's high performance twin tub cmos process technology and was designed for high - speed and low power circuit technology. it is particularly well suited for use in high - density and low power system applications. this device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0v. features fully static operation and tri - state outputs ttl compatible inputs and outputs low power consumption battery backup(ll - part) - . 2.0v(min) data retention standard pin configuration - . 32pin 525mil sop - . 32pin 400mil tsop - ii (standard and reversed) product voltage spee d operation standby current(ua) temperature no. (v) (ns) current /icc (ma) l l ( c ) hy62 u 8400 a 2.7~3.3 70*/ 85 /100 5 20 0~70 hy62 u 8400 a - e 2.7~3.3 70*/ 85 /100 5 30 - 25 ~85 hy62 u 8400 a - i 2.7~3.3 70*/ 85 /100 5 30 - 40~85 note 1. current value is max. * 70 ns is available with 30pf test load pin connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss a17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 a17 a17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss sop tsop - ii (standard) tsop - ii (reversed) pin description block diagram pin name pin function /cs chip select /we write enable /oe output enable a0 ~ a18 address input i/o1 ~ i/o8 data input/output vcc power( 2.7~3.3 v) vss ground memory array 512kx 8 row decoder sense amp write driver data i/o buffer i/o1 i/o8 column decoder add input buffer a0 a18 /cs /oe /we control logic
hy62 u 8400 a series rev 0 7 / apr. 2001 2 ordering information part no. speed power temp package hy62 u 8400 a llg 70 */ 85 /100 ll - part 0~70 c sop hy62 u 8400 a llg - e 70*/ 85 /100 ll - part - 25~85 c sop hy62 u 8400 a llg - i 70*/ 85 /100 ll - part - 40~85 c sop hy62 u 8400 a llt2 70*/ 85 /100 ll - part 0~70 c tsop - ii (standard) hy62 u 8400 a llt2 - e 70*/ 85 /100 ll - part - 25~85 c tsop - ii (standard) hy62 u 8400 a llt2 - i 70*/ 85 /100 ll - part - 40~85 c tsop - ii (standard) hy62 u 8400 a llr2 70*/ 85 /100 ll - part 0~70 c tsop - ii (reversed) hy62 u 8400 a llr2 - e 70*/ 85 /100 ll - part - 25~85 c tsop - ii (reversed) hy62 u 8400 a llr2 - i 70*/ 85 /100 ll - part - 40~85 c tsop - ii (rever sed) * 70 ns is available with 30pf test load absolute maximum rating (1) symbol parameter rating unit vcc, v in, v out power supply, input/output voltage - 0.5 to 4.0 v HY62U8400A 0 to 70 c HY62U8400A - e - 25 to 85 c t a operating temperature HY62U8400A - i - 40 to 85 c t stg storage temperature - 65 to 150 c p d power dissipation 1.0 w i out data output current 50 ma t solder lead soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum rati ngs may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is n ot implied. exposure to the absolute maximum rating conditions for extended period may affect reliablity. truth table /cs /we /oe mode i/o operation power h x x deselected high - z standby l h h output disabled high - z active l h l read data out ac tive l l x write data in active note : 1. h=v ih , l=v il , x=don't care ( v ih or v il )
hy62 u 8400 a series rev 0 7 / apr. 2001 3 recommended dc operating condition t a = 0 ? to 70 ? (normal)/ - 25 c to 85 c ( extended ) / - 40 c to 85 c ( industrial ), unless otherwise specified. symbol parameter m in. typ. max. unit vcc supply voltage 2.7 3.0 3.3 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0.3 v v il input low voltage - 0. 3 (1) - 0.4 v note : 1. v il = - 1.5v for pulse width less than 30ns and not 100% tested. dc electrical characte ristics t a = 0 ? to 70 ? (normal)/ - 25 c to 85 c ( extended ) / - 40 c to 85 c ( industrial ), unless otherwise specified. symbol parameter test condition min typ max unit i li input leakage current vss < v in < vcc - 1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il - 1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il, i i/o = 0ma - 5 ma i cc1 average operating current /cs = v il min duty cycle = 100%, v in = v ih or v il, i i/o = 0ma - 35 ma i sb ttl standby current (ttl input) /cs = v ih v in = v ih or v il - 0.5 ma i sb1 /cs > vcc - 0.2v , l l - - 20 ua standby current (cmos input) v in > vcc - 0.2v or v in < v ss + 0.2v ll - e/i - - 30 ua v ol output low voltage i ol = 2.1ma - - 0.4 v v oh output high voltage i oh = - 1ma 2.2 - - v note : typical values are at vcc = 3.0v, t a = 25 c capacitance temp = 25 c , f= 1.0mhz symbol parameter condition max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v i/o = 0v 8 pf note : this parameter is sampled an d not 100% tested
hy62 u 8400 a series rev 0 7 / apr. 2001 4 ac characteristics t a = 0 ? to 70 ? (normal)/ - 25 c to 85 c ( extended ) / - 40 c to 85 c ( industrial ), unless otherwise specified. - 70* - 85 - 1 0 min. max. min. max. min max. 1 trc read cycle time 70 - 85 - 1 0 0 - ns 2 taa address access time - 70 - 85 - 100 ns 3 tacs chi p select access time - 70 - 85 - 1 0 0 ns 4 toe output enable to output valid - 40 - 45 - 50 ns 5 tclz chip select to output in low z 10 - 1 0 - 10 - ns 6 tolz output enable to output in low z 5 - 5 - 5 - ns 7 tchz chip deselection to output in high z 0 30 0 30 0 30 ns 8 tohz out disable to output in high z 0 30 0 30 0 30 ns 9 toh output hold from address change 10 - 10 - 15 - ns 10 twc write cycle time 70 - 85 - 1 0 0 - ns 11 tcw chip selection to end of write 60 - 70 - 80 - ns 12 taw address vali d to end of write 60 - 70 - 80 - ns 13 tas address set - up time 0 - 0 - 0 - ns 14 twp write pulse width 5 0 - 60 - 70 - ns 15 twr write recovery time 0 - 0 - 0 - ns 16 twhz write to output in high z 0 25 0 3 0 0 35 ns 17 tdw data to write time overlap 30 - 40 - 45 - ns 18 tdh data hold from write time 0 - 0 - 0 - ns 19 tow output active from end of write 5 - 5 - 10 - ns note * 7 0ns is available with 30pf test load ac test conditions t a = 0 ? to 70 ? (normal)/ - 25 c to 85 c ( extended ) / - 40 c to 85 c ( industrial ), unless otherwise specified. parameter value input pulse level 0. 4 v to 2.2v input rise and fall time 5ns input and output timing reference level 1.5v output load tclz,tolz,tchz,tohz ,twhz,tow cl = 5 pf + 1ttl load others cl = 100pf + 1ttl load cl = 3 0pf + 1ttl load ac test loads cl(1) ttl note 1. including jig and scope capacitance read cycle symbol parameter # unit write cycle
hy62 u 8400 a series rev 0 7 / apr. 2001 5 tim ing diagram read cycle 1(note 1 ,4 ) re ad cycle 2(note 1,2, 4 ) trc taa data valid previous data toh toh addr data out read cycle 3(note 1, 2, 4) /cs tacs data valid tclz(3) tchz(3) data out notes: 1. a r ead o ccurs during the overlap of a low /oe, a high /we and a low / cs . 2. /oe = v il 3. transition is measured + 200mv from steady state volta ge. this parameter is sampled and not 100% tested. 4. /cs in high for the standby, low for active addr trc / cs taa tacs toh data valid high - z data out / oe toe tclz (3) t olz (3) t chz (3) tohz (3)
hy62 u 8400 a series rev 0 7 / apr. 2001 6 write cycle 1 (1,4,5,8) (/we controlled) write cycle 2 (note 1,4, 5 ,8 ) (/cs controlled) data valid addr data o ut / cs / we twc tcw twr (2) taw twp data in high - z tas twhz (3,7) tdw tdh tow (5) (6) data valid addr data out / cs / we twc tcw twr (2) taw twp data in tdw tdh high-z high-z tas
hy62 u 8400 a series rev 0 7 / apr. 2001 7 notes: 1. a write occurs during the overlap of a low / we and a low /cs. 2. twr is measured from the earlier of /cs or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured + 200mv from steady state. this parameter is sampled and not 100% tested. 8 . /cs in high for the standby, low for active data retention electric charateristic t a = 0 ? to 70 ? (normal)/ - 25 c to 85 c ( extended ) / - 40 c to 85 c ( industrial ), unless otherwise specified. symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v , 2.0 - - v v in > vcc - 0.2v or v in < 0.2v i ccdr vcc = 3.0v, l l - - 20 ua /cs > vcc - 0.2v , ll - e - - 30 ua data retent ion current v in > vcc - 0.2v or v in < 0.2v ll - i - - 30 ua tcdr chip deselect to data retention time 0 - - ns tr operating recovery time trc(2) - - ns notes: 1. typical values are at the conditio n of t a = 25 c . 2. trc is read cycle time. data retention timing diagram / cs vdr / cs > vcc-0.2v tcdr tr vss vcc 2.7v 2.2v data retention mode
hy62 u 8400 a series rev 0 7 / apr. 2001 8 package information 32pin 400mil thin small outline package standard(t2) 0.404(10.2620) 0.396(10.0580() 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) 0.050bsc (1.2700) 0.017(0.4500) 0.012(0.3050) base plane seating plane 0.047(1.1940) 0.039(0.9910) 0.0059(0.1500) 0.0020(0.0500) 0.0083(0.2100) 0.0047(0.1200) 0.0235(0.5970) 0.0160(0.4060) gage plane 0-5 unit : inch(mm) max. min. 32pin 400mil thin sm all outline package reversed(r2) 0.404(10.2620) 0.396(10.0580) 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) 0.050 bsc (1.2700) 0.017(0.4500) 0.012(0.3050) base plane seating plane 0.047(1.1940) 0.039(0.9910) 0.0059(0.1500) 0.0020(0.0500) 0.0083(0.2100) 0.0047(0.1200) 0.0235(0.5970) 0.0160(0.4060) gage plane 0-5 unit : inch(mm) max. min.
hy62 u 8400 a series rev 0 7 / apr. 2001 9 32pin 525mil small outline package(g) unit : inch(mm) 0.444(11.27 8 ) 0.438(11.125) 0.564(14.326) 0.546(13.868) 0.810(20.574) 0.804(20.42 2 ) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.10 2 ) 0.020(0.508) 0.014(0.356) 0.050(1.27)bsc 0.0125(0.318) 0.0061(0.155) 0.0425(1.0 80 ) 0.0235(0.59 7 ) 0 deg 8 deg
hy62 u 8400 a series rev 0 7 / apr. 2001 10 marking information h y n i x k o r e a h y 6 2 u 8 4 0 0 a y y w w p c c g - s s t h y n i x k o r e a h y 6 2 u 8 4 0 0 a y y w w p c c t 2 - s s t sop tsop - ii package marking example index ? hynix : hynix logo ? korea : origin country ? HY62U8400A : part name ? yy : year ( ex : 00 = year 2000, 01 = year 2001 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code ? cc : power consumption - l : low power - ll : low low power ? g / t2 : package type - g : sop - t2 : tsop - ii ? ss : speed - 85 : 85ns - 10 : 100ns ? t : temperature - blank : commercial ( 0 ~ 70 c ) - e : extended ( - 25 ~ 85 c ) - i : industrial ( - 40 ~ 85 c ) note - capital letter : fixed item - small letter : non - fixed item (except hynix ) h y n i x k o r e a h y n i x k o r e a h y 6 2 u 8 4 0 0 a h y 6 2 u 8 4 0 0 a y y w w p c c g - s s t y y w w p c c g - s s t h y n i x k o r e a h y n i x k o r e a h y 6 2 u 8 4 0 0 a h y 6 2 u 8 4 0 0 a y y w w p c c t 2 - s s t y y w w p c c t 2 - s s t sop tsop - ii package marking example index ? hynix : hynix logo ? korea : origin country ? HY62U8400A : part name ? yy : year ( ex : 00 = year 2000, 01 = year 2001 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code ? cc : power consumption - l : low power - ll : low low power ? g / t2 : package type - g : sop - t2 : tsop - ii ? ss : speed - 85 : 85ns - 10 : 100ns ? t : temperature - blank : commercial ( 0 ~ 70 c ) - e : extended ( - 25 ~ 85 c ) - i : industrial ( - 40 ~ 85 c ) note - capital letter : fixed item - small letter : non - fixed item (except hynix )

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